Clock Generation
Datasheets are available on request only with appropriate non-disclosure agreements.
| Component |
Description |
Process |
| high-speed clock synthesis (plus other applications) PLL |
- [1MHz ≤ Fin ≤ 5MHz]
- [1MHz ≤ Fout ≤ 1000MHz]
- low jitter
- wide bandwidth
- wide division rations
|
TSMC 90nm mixed signal |
| high-speed spread-spectrum PLL |
- [1MHz ≤ Fin ≤ 50MHz]
- [500MHz ≤ Fout ≤ 5000MHz]
- fast settling
|
TSMC 0.18μm mixed signal |
| multi-modulus pre-scalers |
- [10GHz > Fin > 50MHz]
- low insertion delay
|
bipolar |
| ultra-high speed oscillators |
1GHz to 10GHz |
BiCMOS; proprietary |
| 1.2-V, 1.1-GHz, sub-10 ps jitter fractional-N synthesizer |
high speed baseband timing recovery applications; e.g., ADSL |
UMC 0.11μm mixed signal |
|
|